1/8 STA501 september 2003 n minimum input output pulse width distortion n 200m w r dson complementary dmos output stage n cmos compatible logic inputs n thermal protection n thermal warning output n under voltage protection description STA501 is a monolithic dual half bridge stage in mul- tipower bcd technology. the device is particularly designed to make the out- put stage of a mono all-digital high efficiency (ddx?) amplifier capable to deliver 50w @ thd = 10% at v cc 30v output power on 8 w load. the input pins have threshold proportional to ibias pin voltage. powerso36 ordering number: STA501 40v 3.5a double power half bridge audio application circuit c30 1 m f c107 100nf c106 100nf c55 1000 m f c58 100nf c58 100nf r57 10k r59 10k c53 100nf c60 100nf c31 1 m f r104 20 c109 330pf 15 gnd ibias config pwrdn pwrdn fault tri-state th_war th_war +3.3v gnd v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean ina ina inb protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 gnd v cc 14 12 gnd v cc b 13 l113 22 m h l112 22 m h c32 1 m f +v cc c108 470nf c33 1 m f 7 m17 m15 m16 m14 8 9 outa gnda outa v cc a 6 4 2 3 outb gndb d02au1447 outb v cc b 5 n.c. n.c. 16 17 19 31 20 gndsub 1 n.c. 10 n.c. 11 inb 32 c110 100nf c111 100nf r103 6 r102 6 multipower bcd technology
STA501 2/8 pin function n pin description 1 gnd-sub substrate ground 35 ; 36 vcc sign signal positive supply 15 vcc positive supply 12 vcc positive supply 7 vcc positive supply 4 vcc positive supply 14 gnd negative supply 13 gnd negative supply 6 gnd negative supply 5 gnd negative supply 16 ; 17 n.c. 10 ; 11 n.c. 8 ; 9 outa output half bridge 2 ; 3 outb output half bridge 29 gnd 30 gnd 31 ina input of half bridge 32 inb input of half bridge 21 ; 22 vdd 5v regulator referred to ground 33 ; 34 vss 5v regulator referred to +vcc 25 pwrdn stand-by pin 26 tri-state hi-z pin 27 fault fault pin advisor 24 gnd 28 th-war thermal warning advisor 19 gnd-clean logical ground 23 ibias high logical state setting voltage 18 nc not connected 20 gnd-reg ground for regulator vdd
3/8 STA501 functional pin status * : the pin is open collector. to have the high logic value, it needs to be pulled up by a resistor. pin connection pin name logical value ic -status fault 0 fault detected (short circuit, or thermal ..) fault * 1 normal operation tri-state 0 all powers in hi-z state tri-state 1 normal operation pwrdn 0 low absorpion pwrdn 1 normal operation thwar 0 temperature of the ic =130c thwar* 1 normal operation gnd-sub outb outb v cc gnd v cc gnd n.c. n.c. gnd-reg v dd v dd gnd ibias v ss v ss v cc sign v cc sign 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 n.c. gnd-clean d02au1449 n.c v cc n.c. pwrdn fault tri-state 9 8 7 28 29 30 outa th_war 10 27 gnd outa v cc gnd inb gnd 14 12 11 23 25 26 gnd ina 13 24
STA501 4/8 absolute maximum ratings thermal data electrical characteristcs (ibias = 3.3v; vcc = 30v; t amb = 25c unless otherwise specified) symbol parameter value unit v ce dc supply voltage (pin 4,7,12,15) 40 v v max maximum voltage on pins 23 to 32 5.5 v t op operating temperature range 0 to 70 c t stg , t j storage and junction temperature -40 to 150 c symbol parameter min. typ. max. unit t j-case thermal resistance junction to case (thermal pad) 2.5 c/w t jsd thermal shut-down junction temperature 150 c t warn thermal warning temperature 130 c t hsd thermal shut-down hysteresis 25 c symbol parameter test conditions min. typ. max. unit r dson power pchannel/nchannel mosfet rdson id=1a 200 270 m w i dss power pchannel/nchannel leakage idss vcc=35v 50 m a g n power pchannel rdson matching id=1a 95 % g p power nchannel rdson matching id=1a 95 % dt_s low current dead time (static) see test circuit no.1; see fig. 1 10 20 ns dt_d high current dead time (dinamic) l=22 m h; c = 470nf; rl = 8 w id=3.5a; see fig. 3 50 ns t d on turn-on delay time resistive load 100 ns t d off turn-off delay time resistive load 100 ns t r rise time resistive load 25 ns t f fall time resistive load; as fig. 1 25 ns v cc supply voltage operating voltage 10 36 v v in-h high level input voltage ibias/2 +300mv v v in-l low level input voltage ibias/2 -300mv v i in-h hi level input current pin voltage = ibias 1 m a
5/8 STA501 notes: 1. the following table explains the vl, vh variation with ibias logic truth table (see fig. 2) i in-l low level input current pin voltage = 0.3v 1 m a i pwrdn-h hi level pwrdn pin input current ibias = 3.3v 35 m a v l low logical state voltage vl (pin pwrdn, tristate) (note 1) ibias = 3.3v 0.8 v v h high logical state voltage vh (pin pwrdn, tristate) (note 1) ibias = 3.3v 1.7 v i vcc- pwrdn supply current from vcc in power down pwrdn = 0 3 ma i fault output current pins fault -th-warn when fault conditions vpin = 3.3v 1 ma i vcc-hiz supply current from vcc in tri- state vcc=30v; tri-state=0 22 ma i vcc supply current from vcc in operation (both channel switching) input pulse width = 50% duty; switching frequency = 384khz; no lc filters; 80 ma i vcc-q isc (short circuit current limit) 3.5 6 8 a i out-sh undervoltage protection threshold 7 v v ov output minimum pulse width no load 70 150 ns ibias vlmin vhmax unit 2.7 0.7 1.5 v 3.3 0.8 1.7 v 5 0.85 1.85 v tri-state ina inb q1 q2 q3 q4 output mode 0 x x off off off off hi-z 1 0 0 off off on on dump 1 0 1 off on on off negative 1 1 0 on off off on positive 1 1 1 on on off off not used symbol parameter test conditions min. typ. max. unit electrical characteristcs (continued)
STA501 6/8 figure 1. test circuit. figure 2. figure 3. low current dead time = max(dtr,dtf) outy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% iny outy gnd +vcc m58 m57 r 8 w + - v67 = vdc = vcc/2 d02au1448 ina inb +v cc q1 q3 q2 q4 outa gnd outb d02au1450 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 w q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=3.5a iout=3.5a q4 q1 q3 m64 inb m63 d02au1451 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 3.5a in the direction shown in figure l68 22 m l67 22 m outa
7/8 STA501 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.25 3.5 0.128 0.138 a2 3.3 0.13 a4 0.8 1 0.031 0.039 a5 0.2 0.008 a1 0 0.075 0 0.003 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d 15.8 16 0.622 0.630 d1 9.4 9.8 0.37 0.38 d2 1 0.039 e 13.9 14.5 0.547 0.57 e1 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 e4 2.9 3.2 0.114 1.259 e 0.65 0.026 e3 11.05 0.435 g 0 0.075 0 0.003 h 15.5 15.9 0.61 0.625 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 10? (max) s 8? (max) (1) d and e1 do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15mm (0.006) (2) no intrusion allowed inwards the leads. powerso36 (slug up) 7183931
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